Dual rail LCD (Liquid Crystal Display) column drivers commonly use shield circuits (shields) to assure that the output transistors do not exceed a specified maximum voltage. As shown in FIG. 1, by way of example, such shields prevent the transistors from exceeding 8 volts (in this example using 8 volt compliance transistors).
In FIG. 1, DAC=Digital to Analog Converter; UDAC=Upper DAC 10; LDAC=Lower DAC 12; USWITCHES=Upper switches 14; LSWITCHES=Lower switches 16; USHIELD=Upper shield 18; and LSHIELD=Lower shield 20. Upper refers to upper range of the DAC circuit which normally operates between HVDD-AVDD; and Lower refers to lower range which normally operates between 0-HVDD. In the example of FIG. 1, AVDD =16 volts max, and HVDD =8 volts max. Thus, the output at the PAD or node 24 has an output voltage swing between 0 and AVDD which in this example is 16 volts.
In FIG. 1, the transistor devices used in all circuits are 8V compliance transistors. The configuration of the UDAC 10 and LDAC 12, are depicted in greater detail in FIG. 2, in which the body of NMOS transistor 22 could be coupled to the ground (0V) for the lower range. The body of the NMOS transistor 24 can be coupled to HVDD for the upper range while the body of the PMOS transistor 26 could be coupled to HVDD for the lower range and the body of the PMOS transistor 28 can be coupled to AVDD for the upper range. This is the case with the p-substrate isolated technology. In the case of the p-substrate non isolated technology, all of the NMOS' body are tied to ground. The non isolated technology will introduce the body effect and increase the on resistance of the NMOS of the upper DAC hence degrading the speed performance.
The output is taken at 30 for the upper range of the DAC (UDAC) and 32 for the lower range of the DAC (LDAC) as shown. This output is passed to USWITCHES 14 and LSWITCHES 16 respectively to produce switch outputs 34 and 36 respectively. The switches 14 and 16 respectively are switched in a manner such that the lower range is open and the upper range closed when there is a DAC output that is in the upper range, and vice versa when there is an output in the lower range from the DAC.
FIG. 1 also shows that the PAD 24 swings from 0V to AVDD while the OUTUSW and OUTLSW always swings from HVDD to AVDD and 0 to HVDD respectively. This is due to the use of the shields 18 and 20 in order to protect the 8V compliance devices, hence at any given time the voltage across any of the devices won't exceed 8V. The shields 18 and 20 are generally configured as cascode transistors with the gates around HVDD.